As the use of digital data increases, the demand for faster, smaller, and more efficient memory structures increases. One type of memory structure that has recently been developed is a crossbar memory array. A crossbar memory array includes a set of upper parallel wires which intersect a set of lower parallel wires. A programmable memory element configured to store digital data is placed at each intersection of the wires.
A memory array utilizing crossbar architecture is subject to a number of design constraints. One of these constraints limits the number of memory elements which can be placed along a particular wire within the memory array. The number of memory elements is constrained because having too many memory elements along a particular wire makes it more difficult to isolate a particular memory element for reading and writing operations.
For example, particular memory elements within a crossbar array are often read by applying half of a read voltage to one wire connected to the target memory element and the other half of the read voltage to the other wire connected to the target memory element. This applies the full read voltage to the target memory element while only applying half of the read voltage to half-selected memory elements. Half-selected memory elements are those that are positioned along the same line as a fully selected target memory element. When half of the read voltage is applied to the half-selected memory elements, a current is produced which adds to the current sensed by the reading circuitry used to sense the electric current from the target memory element.
Each half-selected memory element contributes a small amount of unwanted current to sensing circuitry used to sense the current flowing through the target memory element. To limit the amount of electric current contributed by the half-selected memory elements, non-linear devices are used. Generally, it is desirable to use memory elements with a high degree of non-linearity. Using devices with a higher degree of non-linearity allows a memory array with more memory elements along a particular wire line to be produced.
Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.